#ifndef _MPI_VO_H_
#define _MPI_VO_H_

#include "mpi_cmd.h"

#ifdef  __cplusplus
extern "C"
{
#endif


#define SGKS_VO_SETUP_NA          (0x00)
#define SGKS_VO_SETUP_VALID       (1 << 0)
#define SGKS_VO_SETUP_CHANGED     (1 << 1)
#define SGKS_VO_SETUP_NEW         (SGKS_VO_SETUP_VALID | SGKS_VO_SETUP_CHANGED)

#define SGKS_VO_CLUT_SIZE                         (256)
#define DSP_OSD_CLUT_DRAM_SIZE       0x400


#define REG_VO_DISPLAY0_CONTROL							  0
#define REG_VO_DISPLAY0_FRAME_SIZE_FIELD0				  0x08
#define REG_VO_DISPLAY0_FRAME_SIZE_FIELD1				  0x0c
#define REG_VO_DISPLAY0_ACTIVE_REGION_START_FIELD0       0x10
#define	REG_VO_DISPLAY0_ACTIVE_REGION_END_0			      0x14
#define REG_VO_DISPLAY0_ACTIVE_REGION_START_FIELD1       0x18 /* read/write */
#define REG_VO_DISPLAY0_ACTIVE_REGION_END_1               0x1C /* read/write */
#define REG_VO_DISPLAY0_BACKGROUND                         0x20 /* write */
#define REG_VO_DISPLAY0_DIGITAL_OUTPUT                     0x24 /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_HSYNC_CONTROL             0x28 /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_VSYNC_START_0             0x2C /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_VSYNC_END_0               0x30 /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_VSYNC_START_1                     0x34 /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_VSYNC_END_1                         0x38 /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_656_VBIT                                0x3C /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_656_SAV_START                     0x40 /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN0                   0x44 /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN1                   0x48 /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN2                   0x4C /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN3                   0x50 /* read/write */
#define REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_0                         0x54 /* write */
#define REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_1                         0x58 /* write */
#define REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_2                         0x5C /* write */
#define REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_3                         0x60 /* write */
#define REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_4                         0x64 /* write */
#define REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_5                         0x68 /* write */
#define REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_6                         0x6C /* write */
#define REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_7                         0x70 /* write */
#define REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_8                         0x74 /* write */
#define REG_VO_DISPLAY0_VOUT_VOUT_SYNC                                  0x15C /* read/write */
#define REG_VO_DISPLAY0_INPUT_STREAM_ENABLES                       0x160 /* read/write */
#define REG_VO_DISPLAY0_INPUT_SYNC_CONTROL                  		 0x164 /* read/write */
#define REG_VO_DISPLAY0_OUTPUT_SYNC_CONTROL                	 0x168 /* read/write */
#define REG_VO_DISPLAY0_STREAM_CONTROL                      		 0x16C /* read/write */
#define REG_VO_DISPLAY0_FRAME_ENABLE                        		 0x170 /* read/write */


#define REG_VO_DISPLAY0_BASE                                  			REG_VO_DISPLAY0_CONTROL
#define OFFSET_REG_VO_DISPLAY0_CONTROL                        		((REG_VO_DISPLAY0_CONTROL                   - REG_VO_DISPLAY0_BASE)>>2)  //00
#define OFFSET_REG_VO_DISPLAY0_FRAME_SIZE_FIELD0              ((REG_VO_DISPLAY0_FRAME_SIZE_FIELD0         - REG_VO_DISPLAY0_BASE)>>2)  //08
#define OFFSET_REG_VO_DISPLAY0_FRAME_SIZE_FIELD1              ((REG_VO_DISPLAY0_FRAME_SIZE_FIELD1         - REG_VO_DISPLAY0_BASE)>>2)  //0c
#define OFFSET_REG_VO_DISPLAY0_ACTIVE_REGION_START_FIELD0     ((REG_VO_DISPLAY0_ACTIVE_REGION_START_FIELD0- REG_VO_DISPLAY0_BASE)>>2)  //10
#define OFFSET_REG_VO_DISPLAY0_ACTIVE_REGION_END_0            ((REG_VO_DISPLAY0_ACTIVE_REGION_END_0       - REG_VO_DISPLAY0_BASE)>>2)  //14
#define OFFSET_REG_VO_DISPLAY0_ACTIVE_REGION_START_FIELD1     ((REG_VO_DISPLAY0_ACTIVE_REGION_START_FIELD1- REG_VO_DISPLAY0_BASE)>>2)  //18
#define OFFSET_REG_VO_DISPLAY0_ACTIVE_REGION_END_1            ((REG_VO_DISPLAY0_ACTIVE_REGION_END_1       - REG_VO_DISPLAY0_BASE)>>2)  //1c
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_OUTPUT                 	  ((REG_VO_DISPLAY0_DIGITAL_OUTPUT            - REG_VO_DISPLAY0_BASE)>>2)  //24
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_HSYNC_CONTROL          ((REG_VO_DISPLAY0_DIGITAL_HSYNC_CONTROL     - REG_VO_DISPLAY0_BASE)>>2)  //28
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_VSYNC_START_0          ((REG_VO_DISPLAY0_DIGITAL_VSYNC_START_0     - REG_VO_DISPLAY0_BASE)>>2)  //2c
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_VSYNC_END_0            ((REG_VO_DISPLAY0_DIGITAL_VSYNC_END_0       - REG_VO_DISPLAY0_BASE)>>2)  //30
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_VSYNC_START_1          ((REG_VO_DISPLAY0_DIGITAL_VSYNC_START_1     - REG_VO_DISPLAY0_BASE)>>2)  //34
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_VSYNC_END_1            ((REG_VO_DISPLAY0_DIGITAL_VSYNC_END_1       - REG_VO_DISPLAY0_BASE)>>2)  //38
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN0         ((REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN0    - REG_VO_DISPLAY0_BASE)>>2)  //44
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN1         ((REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN1    - REG_VO_DISPLAY0_BASE)>>2)  //48
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN2         ((REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN2    - REG_VO_DISPLAY0_BASE)>>2)  //4c
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN3         ((REG_VO_DISPLAY0_DIGITAL_CLOCK_PATTERN3    - REG_VO_DISPLAY0_BASE)>>2)  //50
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_0            ((REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_0       - REG_VO_DISPLAY0_BASE)>>2)  //54
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_1            ((REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_1       - REG_VO_DISPLAY0_BASE)>>2)  //58
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_2            ((REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_2       - REG_VO_DISPLAY0_BASE)>>2)  //5c
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_3            ((REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_3       - REG_VO_DISPLAY0_BASE)>>2)  //60
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_4            ((REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_4       - REG_VO_DISPLAY0_BASE)>>2)  //64
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_5            ((REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_5       - REG_VO_DISPLAY0_BASE)>>2)  //68
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_6            ((REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_6       - REG_VO_DISPLAY0_BASE)>>2)  //6c
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_7            ((REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_7       - REG_VO_DISPLAY0_BASE)>>2)  //70
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_8            ((REG_VO_DISPLAY0_DIGITAL_CSC_PARAM_8       - REG_VO_DISPLAY0_BASE)>>2)  //74
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_656_VBIT                    ((REG_VO_DISPLAY0_DIGITAL_656_VBIT           - REG_VO_DISPLAY0_BASE)>>2)
#define OFFSET_REG_VO_DISPLAY0_DIGITAL_656_SAV_START          ((REG_VO_DISPLAY0_DIGITAL_656_SAV_START     - REG_VO_DISPLAY0_BASE)>>2)

typedef enum sgks_vo_source_status
{
	SGKS_VO_SOURCE_STATUS_IDLE = 0,
	SGKS_VO_SOURCE_STATUS_RUNNING = 1,
	SGKS_VO_SOURCE_STATUS_SUSPENDED = 2,
} sgks_vo_source_status_e;

typedef union
{
	struct
	{
#define RST_PHASE_ACCUMULATOR_DIS       0
#define RST_PHASE_ACCUMULATOR_ENA       1
		u32 t_reset_fsc     :  1;   /* [0]  */

#define PHASE_OFFSET_DIS                0
#define PHASE_OFFSET_ENA                1
		u32 t_offset_phase  :  1;   /* [1] */

#define INVERT_COMP_DIS                 0
#define INVERT_COMP_ENA                 1
		u32 v_invert        :  1;   /* [2] */
		u32 u_invert        :  1;   /* [3] */

		u32 reserved        :  4;   /* [7:6] */
		u32 unused          : 24;   /*[31:8] */
	} s;
	u32 w;
} tv40_t;

typedef union
{
	struct
	{
		u32 t_ygain_val     :  1;   /* [0] */
		u32 t_sel_ylpf      :  1;   /* [1] Luma LPF select */
		u32 t_ydel_adj      :  3;   /* [4:2] Adjust Y delay */
		u32 y_colorbar_en   :  1;   /* [5] Enable internal color bar gen */
		u32 y_interp        :  2;   /* [7:6] choose luma interpolatino mode */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv46_t;

typedef union
{
	struct
	{
		u32 pwr_dwn_c_dac   :  1;   /* [0] */
		u32 pwr_dwn_y_dac   :  1;   /* [1] */
		u32 pwr_dwn_cv_dac  :  1;   /* [2] */
		u32 sel_yuv         :  1;   /* [3] */
		u32 reserved        :  4;   /* [7:4] */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv47_t;

typedef union
{
	struct
	{
		u32 sel_c_gain      :  1;   /* [0] */
		u32 pal_c_lpf       :  1;   /* [1] */
		u32 reserved        :  4;   /* [7:4] */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv52_t;

typedef union
{
	struct
	{
		u32 y_tencd_mode    :  3;   /* [2:0] select TV standard */
		u32 y_tsyn_mode     :  3;   /* [5:3] master/slave/timecode ysnc
                                       mode and input format select */
		u32 t_vsync_phs     :  1;   /* [6] select phase of Vsync in/out */
		u32 t_hsync_phs     :  1;   /* [7] select phase of hsync in/out */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv56_t;

typedef union
{
	struct
	{
		u32 vso             :  2;   /* [1:0] vertical sync offset MSBs */
		u32 unused          :  2;   /* [3:2] */
		u32 t_psync_phs     :  1;   /* [4] select phase of field sync in/out */
		u32 t_psync_enb     :  1;   /* [5] enable ext_vsync_in as
                                       field sync input */
		u32 clk_phs         :  2;   /* [7:6] 6.75/13.5 MHz phase adjust */
		u32 unused2         : 24;   /* [31:8] */
	} s;
	u32 w;
} tv57_t;

typedef union
{
	struct
	{
		u32 cs_ln           :  2;   /* [1:0] */
		u32 cs_num          :  3;   /* [4:2] */
		u32 cs_sp           :  3;   /* [7:5] */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv77_t;

typedef union
{
	struct
	{
		u32 bst_zone_sw2    :  4;   /* [3:0] */
		u32 bst_zone_sw1    :  4;   /* [7:4] */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv88_t;

typedef union
{
	struct
	{
		u32 bz_invert_en    :  3;   /* [2:0] */
		u32 adv_bs_en       :  1;   /* [3] */
		u32 bz3_end         :  4;   /* [7:4] */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv89_t;

typedef union
{
	struct
	{
		u32 fsc_tst_en      :  1;   /* [0] */
		u32 sel_sin         :  1;   /* [1] */
		u32 reserved        :  6;   /* [7:2] */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv96_t;

typedef union
{
	struct
	{
		u32 dig_out_en      :  2;   /* [1:0] */
		u32 sel_dac_tst     :  1;   /* [2] */
		u32 sin_cos_en      :  1;   /* [3] */
		u32 ygain_off       :  1;   /* [4] */
		u32 sel_y_lpf       :  1;   /* [5] */
		u32 byp_y_ups       :  1;   /* [6] */
		u32 reserved        :  1;   /* [7] */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv97_t;

typedef union
{
	struct
	{
		u32 cgain_off       :  1;   /* [0] */
		u32 byp_c_lpf       :  1;   /* [1] */
		u32 byp_c_ups       :  1;   /* [2] */
		u32 reserved        :  5;   /* [7:3] */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv99_t;

//read only
typedef union
{
	struct
	{
		u32 ed_stat_full    :  1;   /* [0] */
		u32 cc_stat_full    :  1;   /* [1] */
		u32 reserved        :  6;   /* [7:2] */
		u32 unused          : 24;   /* [31:8] */
	} s;
	u32 w;
} tv128_t;


typedef struct sgks_dram_tv
{
	u32     unsued1[32];
	u32     phi_7_0;
	u32     phi_15_8;
	u32     phi_16_23;
	u32     phi_24_31;
	u32     sctoh_7_0;
	u32     sctoh_15_8;
	u32     sctoh_23_16;
	u32     sctoh_31_24;
	tv40_t  tv_40;
	u32     unused2;
	u32     black_lvl;
	u32     blank_lvl;
	u32     clamp_lvl;
	u32     sync_lvl;
	tv46_t  tv_46;
	tv47_t  tv_47;
	u32     unused3[2];
	u32     nba;
	u32     pba;
	tv52_t  tv_52;
	u32     unused4[3];
	tv56_t  tv_56;
	tv57_t  tv_57;
	u32     vso_7_0;
	u32     hso_10_8;
	u32     hso_7_0;
	u32     hcl_9_8;
	u32     hcl_7_0;
	u32     unused5[2];
	u32     ccd_odd_15_8;
	u32     ccd_odd_7_0;
	u32     ccd_even_15_8;
	u32     ccd_even_7_0;
	u32     cc_enbl;
	u32     unused6[2];
	u32     mvfcr;
	u32     mvcsl1_5_0;
	u32     mvcls1_5_0;
	u32     mvcsl2_5_0;
	u32     mvcls2_5_0;
	tv77_t  tv_77;
	u32     mvpsd_5_0;
	u32     mvpsl_5_0;
	u32     mvpss_5_0;
	u32     mvpsls_14_8;
	u32     mvpsls_7_0;
	u32     mvpsfs_14_8;
	u32     mvpsfs;
	u32     mvpsagca;
	u32     mvpsagcb;
	u32     mveofbpc;
	tv88_t  tv_88;
	tv89_t  tv_89;
	u32     mvpcslimd_7_0;
	u32     mvpcslimd_9_8;
	u32     unused7[4];
	tv96_t  tv_96;
	tv97_t  tv_97;
	u32     unused8;
	tv99_t  tv_99;
	u32     mvtms_3_0;
	u32     unused9[8];
	u32     hlr_9_8;
	u32     hlr_7_0;
	u32     vsmr_4_0;
	u32     unused10[4];
	u32     tv116;
	u32     tv117;
	u32     tv118;
	u32     tv119;
	u32     tv120;
	u32     tv121;
	u32     tv122;
	u32     tv123;
	u32     tv124;
	u32     unused11[3];
	tv128_t tv_r128;
} sgks_dram_tv_s;



typedef struct sgks_vd_ctrl
{
#define    VD_NON_FIXED         0x0
#define    VD_480I60            0x1
#define    VD_480P60            0x2
#define    VD_576I50            0x3
#define    VD_576P50            0x4
#define    VD_720P60            0x5
#define    VD_720P50            0x6
#define    VD_1080I60           0x7
#define    VD_1080I50           0x8
#define    VD_1080I48_1080PSF24 0x9
#define    VD_1080P60           0xa     /* only for HDMI mode */
#define    VD_1080P50           0xb     /* only for HDMI mode */
#define    VD_1080P24           0xc     /* test mode */
#define    VD_1080P25           0xd     /* test mode */
#define    VD_1080P30           0xe     /* test mode */
	u32 vid_format          :  5;       /* [4:0] Fixed Format Select */

#define VD_PROGRESSIVE          0
#define VD_INTERLACE            1
	u32 interlace           :  1;       /* [5:5] Interlace Enable */

#define VD_REVERSE_DIS          0
#define VD_REVERSE_ENA          1
	u32 reverse_mode        :  1;       /* [6:6] Reverse Mode Enable, Video Data
                                       is horizontally reversed */

	u32 reserved1           : 18;       /* [24:7] Reserved */

#define SYNC_TO_VO_DIS          0
#define SYNC_TO_VO_ENA          1
	u32 sync_to_vo          :  1;       /* [25:25] VO-VO Sync Enable */

#define SYNC_TO_VI_DIS          0
#define SYNC_TO_VI_ENA          1
	u32 sync_to_vi          :  1;       /* [26:26] VI-VO Sync Enable */

#define VD_DIGITAL_DIS        0
#define VD_DIGITAL_ENA        1
	u32 digital_out         :  1;       /* [27:27] Digital Output Enable */

#define VD_ANALOG_DIS        0
#define VD_ANALOG_ENA        1
	u32 analog_out          :  1;       /* [28:28] Analog Output Enable */

#define VD_HDMI_DIS        0
#define VD_HDMI_ENA        1
	u32 hdmi_out            :  1;       /* [29:29] HDMI Output Enable */

	u32 tv_reset            :  1;       /* [30:30] DVE Soft Reset */

	u32 display_reset       :  1;       /* [31:31] Software Reset */
} sgks_vd_ctrl_s;



typedef union
{
	sgks_vd_ctrl_s s;
	u32 w;
} sgks_vd_control_s;

typedef union
{
	struct
	{
		u32 hdmi_field          :  1;   /* [0] HDMI Field */
		u32 analog_field        :  1;   /* [1] Analog Fied */
		u32 digital_field       :  1;   /* [2] Digital Field */
		u32 reserved            : 24;   /* [26:3] */
		u32 hdmi_uf             :  1;   /* [27] HDMI Underflow */
		u32 analog_uf           :  1;   /* [28] Analog Underflow */
		u32 digital_uf          :  1;   /* [29] Digital Underflow */
		u32 tv_config_ready     :  1;   /* [30] SDTV Configuration Ready */
		u32 reset_complete      :  1;   /* [31] Reset Complete */
	} s;
	u32 w;
} sgks_vd_status_s;

typedef union
{
	struct
	{
		u32 v                   : 14;   /* [13:0]  num of hync's per vsync */
		u32 reserved1           :  2;   /* [15:14] */
		u32 h                   : 14;   /* [29:16] num of CLK/DCLK per hsync */
		u32 reserved2           :  2;   /* [31:30] */
	} s;
	u32 w;
} sgks_vd_hv_s;


typedef union
{
	struct
	{
		u32 v                   : 14;   /* [13:0]  num of hync's per vsync */
		u32 reserved            : 18;   /* [31:14] */
	} s;
	u32 w;
} sgks_vd_v1_s;


typedef union
{
	struct
	{
		u32 startrow            : 14;   /* [13:0]  vertical starting position
                                           of active display region */
		u32 reserved1           :  2;   /* [15:14] */
		u32 startcol            : 14;   /* [29:16] horizontal starting position
                                           of active display region */
		u32 reserved2           :  2;   /* [31:30] */
	} s;
	u32 w;
} sgks_vd_actstart_s;

typedef union
{
	struct
	{
		u32 endrow              : 14;   /* [13:0]  last line position
                                           of active display region */
		u32 reserved1           :  2;   /* [15:14] */
		u32 endcol              : 14;   /* [29:16] last pixel of active column
                                           of active display region */
		u32 reserved2           :  2;   /* [31:30] */
	} s;
	u32 w;
} sgks_vd_actend_s;


typedef union
{
	struct
	{
		u32 cr                  :  8;   /* [7:0]  background Cr value */
		u32 cb                  :  8;   /* [15:8]  background Cb value */
		u32 y                   :  8;   /* [23:16] background Y value */
		u32 reserved            :  8;   /* [31:24] */
	} s;
	u32 w;
} sgks_vd_bg_s;

// Digital/LCD
typedef union
{
	struct
	{
#define LCD_ACT_LOW                 0
#define LCD_ACT_HIGH                1
		u32 hspol               :  1;   /* [0:0] Digital Hsync Polarity */

		u32 vspol               :  1;   /* [1:1] Digital Vsync Polarity */

#define LCD_CLK_UNDIVIDED           0
#define LCD_CLK_DIVIDED             1
		u32 clk_src             :  1;   /* [2:2] Digital Clock Output Divider */

#define LCD_CLK_DIV_DIS             0
#define LCD_CLK_DIV_ENA             1
		u32 divider_en          :  1;   /* [3:3] Digital Clock Divider Enable */

#define LCD_CLK_VLD_RISING          0
#define LCD_CLK_VLD_FALLING         1
		u32 clk_edge            :  1;   /* [4:4] Digital Clock Edge Select */

#define LCD_CLK_NORMAL              0
#define LCD_CLK_DISABLE             1
		u32 clk_dis             :  1;   /* [5:5] Digital Clock Disable */

		u32 div_ptn_len         :  7;   /* [12:6] Digital Clock Divider Pattern Width */

		u32 mipi_config         :  6;   /* [18:13] MIPI Configuration */

		u32 reserved            :  2;   /* [20:19] Reserved */

#define VO_SEQ_R0_G1_B2             0
#define VO_SEQ_R0_B1_G2             1
#define VO_SEQ_G0_R1_B2             2
#define VO_SEQ_G0_B1_R2             3
#define VO_SEQ_B0_R1_G2             4
#define VO_SEQ_B0_G1_R2             5
#define VO_SEQ_R0_G1                0
#define VO_SEQ_G0_R1                2
#define VO_SEQ_G0_B1                3
#define VO_SEQ_B0_G1                5
		u32 seqe                :  3;   /* [23:21] Color Sequence Even Lines */

		u32 seqo                :  3;   /* [26:24] Color Sequence Odd Lines */


#define LCD_MODE_1COLOR             0
#define LCD_MODE_3COLORS            1
#define LCD_MODE_3COLORS_DUMMY      2
#define LCD_MODE_RGB565             3
#define LCD_MODE_656                4
#define LCD_MODE_601_16BITS         5
#define LCD_MODE_601_24BITS         6
#define LCD_MODE_601_8BITS          7
#define LCD_MODE_BAYER_PATTERN      8
#define LCD_MODE_MIPI_YUV422        9
#define LCD_MODE_MIPI_RGB565       10
#define LCD_MODE_MIPI_RAW8         11
#define LCD_MODE_MIPI_RGB888       12
		u32 mode                :  5;   /* [31:27] Digital Output Mode */
	} s;
	u32 w;
} sgks_lcd_control_s;


typedef union
{
	struct
	{
		u32 hsyncend            : 14;   /* [13:0]  Hsync end column */
		u32 reserved1           :  2;   /* [15:14] Reserved */
		u32 hsyncstart          : 14;   /* [29:16] Hsync start column */
		u32 reserved2           :  2;   /* [31:30] Reserved */
	} s;
	u32 w;
} sgks_vd_hsync_s;



typedef union
{
	struct
	{
		u32 vsyncstart_row      : 14;   /* [13:0]  Vsync start row */
		u32 reserved1           :  2;   /* [15:14] Reserved */
		u32 vsyncstart_column   : 14;   /* [29:16] Vsync start column */
		u32 reserved2           :  2;   /* [31:30] Reserved */
	} s;
	u32 w;
} sgks_vd_vsync_start_s;

typedef union
{
	struct
	{
		u32 vsyncend_row        : 14;   /* [13:0]  Vsync end row */
		u32 reserved1           :  2;   /* [15:14] Reserved */
		u32 vsyncend_column     : 14;   /* [29:16] Vsync end column */
		u32 reserved2           :  2;   /* [31:30] Reserved */
	} s;
	u32 w;
} sgks_vd_vsync_end_s;


typedef union
{
	struct
	{
		u32 vbit_end_row        : 14;   /* [13:0]  656 V bit end row */
		u32 reserved1           :  2;   /* [15:14] Reserved */
		u32 vbit_start_row      : 14;   /* [29:16] 656 V bit start row */
		u32 reserved2           :  2;   /* [31:30] Reserved */
	} s;
	u32 w;
} sgks_lcd_656_vbit_s;



typedef union
{
	struct
	{
		u32 sav_start           : 14;   /* [13:0]  SAV Code Start Location */
		u32 reserved            : 18;   /* [31:14] Reserved */
	} s;
	u32 w;
} sgks_lcd_656_sav_start_s;


typedef union
{
	struct
	{
#define ANALOG_ACT_LOW              0
#define ANALOG_ACT_HIGH             1
		u32 hspol               :  1;   /* [0:0] Digital Hsync Polarity */
		u32 vspol               :  1;   /* [1:1] Digital Vsync Polarity */
		u32 reserved            :  30;    /* [31:2] Reserved */
	} s;
	u32 w;
} sgks_analog_control_s;

typedef union
{
	struct
	{
		u32 vbi_0_voltage       : 10;   /* [9:0] VBI Zero Level */
		u32 vbi_1_voltage       : 10;   /* [19:10] VBI One Level */
		u32 cpb                 :  7;   /* [26:20] VBI Repeat Count */

#define HD_CVBS_SD              0
#define COMP_SD                 1
		u32 sd_comp             :  1;   /* [27:27] SD Component */

		u32 reserved            :  4;   /* [31:28] Reserved */
	} s;
	u32 w;
} sgks_vd_vbi_s;

typedef union
{
	struct
	{
		u32 start_row_0         : 14;   /* [13:0] VBI start row field 0 */
		u32 reserved1           :  2;   /* [15:14] Reserved */
		u32 start_row_1         : 14;   /* [29:16] VBI start row field 1 */
		u32 reserved2           :  2;   /* [31:30] Reserved */
	} s;
	u32 w;
} sgks_vd_vbi_row_s;

typedef union
{
	struct
	{
		u32 end_col             : 14;   /* [13:0] VBI end column */
		u32 reserved1           :  2;   /* [15:14] Reserved */
		u32 start_col           : 14;   /* [29:16] VBI start column */
		u32 reserved2           :  2;   /* [31:30] Reserved */
	} s;
	u32 w;
} sgks_vd_vbi_col_s;


typedef union
{
	struct
	{
		u32 y                   : 11;   /* [10:0] SD Scale Y Coefficient */
		u32 reserved1           :  5;   /* [15:11] Reserved */
		u32 scale_en            :  1;   /* [16:16] SD Scale Enable */
		u32 reserved2           : 15;   /* [31:17] Reserved */
	} s;
	u32 w;
} sgks_vd_sd_scale_y_s;

typedef union
{
	struct
	{
		u32 pr                  : 11;   /* [10:0] SD Scale Pr Coefficient */
		u32 reserved1           :  5;   /* [15:11] Reserved */
		u32 pb                  : 11;   /* [26:16] SD Scale Pb Coefficient */
		u32 reserved2           :  5;   /* [31:27] Reserved */
	} s;
	u32 w;
} sgks_vd_sd_scale_pbpr_s;

typedef union
{
	struct
	{
#define HDMI_ACT_LOW                0
#define HDMI_ACT_HIGH               1
		u32 hspol               :  1;   /* [0:0] Digital Hsync Polarity */
		u32 vspol               :  1;   /* [1:1] Digital Vsync Polarity */

		u32 reserved            : 27;   /* [28:2] Reserved */

#define HDMI_MODE_YCBCR_444         0
#define HDMI_MODE_RGB_444           1
#define HDMI_MODE_YC_422            2
		u32 mode                :  3;   /* [31:29] HDMI Output Mode */
	} s;
	u32 w;
} sgks_hdmi_control_s;


typedef union
{
	struct
	{
		u32 start_row           : 14;   /* [13:0] Display A/B Start Row */
		u32 reserved1           :  2;   /* [15:14]  Reserved */
		u32 field               :  1;   /* [16:16] Field Select */
		u32 reserved2           : 15;   /* [31:17] Reserved */
	} s;
	u32 w;
} sgks_vd_vo_sync_s;

typedef union
{
	struct
	{
		u32 input_select        :  1;   /* [0] Enables input from SMEM */
		u32 reserved            : 31;   /* [31:1]  Reserved */
	} s;
	u32 w;
} sgks_vd_input_stream_enable_s;


typedef struct sgks_dram_osd
{
	u32 osd_buf_dram_addr;
	u16 osd_buf_pitch;
	u8 osd_buf_repeat_field;
	u8 reserved;
	u8 reserved2[24];
} sgks_dram_osd_s;


typedef struct sgks_dram_display
{
	// Global
	sgks_vd_control_s             d_control;
	sgks_vd_status_s              d_status;
	sgks_vd_hv_s                  d_frame_size;
	sgks_vd_v1_s                  d_frame_height_field_1;
	sgks_vd_actstart_s            d_active_region_start_0;
	sgks_vd_actend_s              d_active_region_end_0;
	sgks_vd_actstart_s            d_active_region_start_1;
	sgks_vd_actend_s              d_active_region_end_1;
	sgks_vd_bg_s                  d_background;

	// Digital
	sgks_lcd_control_s            d_digital_output_mode;
	sgks_vd_hsync_s               d_digital_hsync_control;
	sgks_vd_vsync_start_s         d_digital_vsync_start_0;
	sgks_vd_vsync_end_s           d_digital_vsync_end_0;
	sgks_vd_vsync_start_s         d_digital_vsync_start_1;
	sgks_vd_vsync_end_s           d_digital_vsync_end_1;
	sgks_lcd_656_vbit_s           d_digital_656_vbit;
	sgks_lcd_656_sav_start_s      d_digital_656_sav_start;
	u32                         d_digital_clock_pattern_0;
	u32                         d_digital_clock_pattern_1;
	u32                         d_digital_clock_pattern_2;
	u32                         d_digital_clock_pattern_3;
	u32                         d_digital_csc_param_0;
	u32                         d_digital_csc_param_1;
	u32                         d_digital_csc_param_2;
	u32                         d_digital_csc_param_3;
	u32                         d_digital_csc_param_4;
	u32                         d_digital_csc_param_5;
	u32                         d_digital_csc_param_6;
	u32                         d_digital_csc_param_7;
	u32                         d_digital_csc_param_8;

	// Analog
	sgks_analog_control_s         d_analog_output_mode;
	sgks_vd_hsync_s               d_analog_hsync_control;
	sgks_vd_vsync_start_s         d_analog_vsync_start_0;
	sgks_vd_vsync_end_s           d_analog_vsync_end_0;
	sgks_vd_vsync_start_s         d_analog_vsync_start_1;
	sgks_vd_vsync_end_s           d_analog_vsync_end_1;
	sgks_vd_vbi_s                 d_analog_vbi_control;
	sgks_vd_vbi_row_s             d_analog_vbi_start_v;
	sgks_vd_vbi_col_s             d_analog_vbi_h;
	u32                         d_analog_vbi_data0;
	u32                         d_analog_vbi_data1;
	u32                         d_analog_vbi_data2;
	u32                         d_analog_vbi_data3;
	u32                         d_analog_vbi_data4;
	u32                         d_analog_vbi_data5;
	u32                         d_analog_vbi_data6;
	u32                         d_analog_vbi_data7;
	u32                         d_analog_vbi_data8;
	u32                         d_analog_vbi_data9;
	u32                         d_analog_vbi_data10;
	u32                         d_analog_vbi_data11;
	u32                         d_analog_csc_param_0;
	u32                         d_analog_csc_param_1;
	u32                         d_analog_csc_param_2;
	u32                         d_analog_csc_param_3;
	u32                         d_analog_csc_param_4;
	u32                         d_analog_csc_param_5;
	u32                         d_analog_csc_2_param_0;
	u32                         d_analog_csc_2_param_1;
	u32                         d_analog_csc_2_param_2;
	u32                         d_analog_csc_2_param_3;
	u32                         d_analog_csc_2_param_4;
	u32                         d_analog_csc_2_param_5;
	sgks_vd_sd_scale_y_s          d_analog_sd_scale_y;
	sgks_vd_sd_scale_pbpr_s       d_analog_sd_scale_pbpr;

	// HDMI
	sgks_hdmi_control_s           d_hdmi_output_mode;
	sgks_vd_hsync_s               d_hdmi_hsync_control;
	sgks_vd_vsync_start_s         d_hdmi_vsync_start_0;
	sgks_vd_vsync_end_s           d_hdmi_vsync_end_0;
	sgks_vd_vsync_start_s         d_hdmi_vsync_start_1;
	sgks_vd_vsync_end_s           d_hdmi_vsync_end_1;
	u32                         d_hdmi_csc_param_0;
	u32                         d_hdmi_csc_param_1;
	u32                         d_hdmi_csc_param_2;
	u32                         d_hdmi_csc_param_3;
	u32                         d_hdmi_csc_param_4;
	u32                         d_hdmi_csc_param_5;
	u32                         d_hdmi_csc_param_6;
	u32                         d_hdmi_csc_param_7;
	u32                         d_hdmi_csc_param_8;

	u32                         unused[8];

	sgks_vd_vo_sync_s             d_vo_vo_sync;
	sgks_vd_input_stream_enable_s d_input_stream_enable;
	u32                           d_input_sync_control;
	u32                       d_output_sync_control;
	u32                       d_stream_control;
	u32                       d_frame_enable;
} sgks_dram_display_s;

typedef struct sgks_vo_hv_size_info
{
	u16 hsize;
	u16 vtsize;    //vsize for progressive
	u16 vbsize;
} sgks_vo_hv_size_info_s;


typedef struct sgks_vo_window_info
{
	u16 start_x;
	u16 start_y;
	u16 end_x;
	u16 end_y;
	u16 width;
	u16 field_reverse;
} sgks_vo_window_info_s;

typedef struct sgks_video_source_clock_setup
{
	u32                src;
	u32                freq_hz;
} sgks_video_source_clock_setup_s;

typedef struct sgks_vd_config
{
	sgks_vd_control_s             d_control;
	sgks_lcd_control_s            d_digital_output_mode;
	sgks_analog_control_s         d_analog_output_mode;
	sgks_hdmi_control_s           d_hdmi_output_mode;
} sgks_vd_config_s;



typedef struct sgks_vo_hv_sync_info
{
	u16 hsync_start;
	u16 hsync_end;
	u16 vtsync_start;
	u16 vtsync_end;
	u16 vbsync_start;
	u16 vbsync_end;

	u16 vtsync_start_row;
	u16 vtsync_start_col;
	u16 vtsync_end_row;
	u16 vtsync_end_col;
	u16 vbsync_start_row;
	u16 vbsync_start_col;
	u16 vbsync_end_row;
	u16 vbsync_end_col;

	sgks_vo_sink_type_e sink_type;
} sgks_vo_hv_sync_info_s;

typedef enum sgks_video_source_csc_mode_info
{
	SGKS_VIDEO_SOURCE_CSC_YUVSD2YUVHD     = 0,    /* YUV601 -> YUV709 */
	SGKS_VIDEO_SOURCE_CSC_YUVSD2YUVSD     = 1,    /* YUV601 -> YUV601 */
	SGKS_VIDEO_SOURCE_CSC_YUVSD2RGB       = 2,    /* YUV601 -> RGB    */
	SGKS_VIDEO_SOURCE_CSC_YUVHD2YUVSD     = 3,    /* YUV709 -> YUV601 */
	SGKS_VIDEO_SOURCE_CSC_YUVHD2YUVHD     = 4,    /* YUV709 -> YUV709 */
	SGKS_VIDEO_SOURCE_CSC_YUVHD2RGB       = 5,    /* YUV709 -> RGB    */
	SGKS_VIDEO_SOURCE_CSC_RGB2RGB         = 6,    /* RGB    -> RGB */
	SGKS_VIDEO_SOURCE_CSC_RGB2YUV         = 7,    /* RGB    -> YUV */
	SGKS_VIDEO_SOURCE_CSC_RGB2YUV_12BITS  = 8,    /* RGB    -> YUV_12bits */

	SGKS_VIDEO_SOURCE_CSC_ANALOG_SD       = 0,
	SGKS_VIDEO_SOURCE_CSC_ANALOG_HD       = 1,
} sgks_video_source_csc_mode_info_e;


typedef enum sgks_video_source_csc_clamp_info
{
	SGKS_VIDEO_SOURCE_CSC_DATARANGE_ANALOG_HD_FULL        = 0,
	SGKS_VIDEO_SOURCE_CSC_DATARANGE_ANALOG_SD_FULL        = 1,
	SGKS_VIDEO_SOURCE_CSC_DATARANGE_DIGITAL_HD_FULL       = 2,
	SGKS_VIDEO_SOURCE_CSC_DATARANGE_DIGITAL_SD_FULL       = 3,
	SGKS_VIDEO_SOURCE_CSC_DATARANGE_ANALOG_HD_CLAMP       = 4,
	SGKS_VIDEO_SOURCE_CSC_DATARANGE_ANALOG_SD_CLAMP       = 5,
	SGKS_VIDEO_SOURCE_CSC_DATARANGE_DIGITAL_HD_CLAMP      = 6,
	SGKS_VIDEO_SOURCE_CSC_DATARANGE_DIGITAL_SD_CLAMP      = 7,
	SGKS_VIDEO_SOURCE_CSC_DATARANGE_HDMI_YCBCR422_CLAMP   = 8,

	SGKS_VIDEO_SOURCE_CSC_ANALOG_CLAMP_SD                 = 0,
	SGKS_VIDEO_SOURCE_CSC_ANALOG_CLAMP_HD                 = 1,
	SGKS_VIDEO_SOURCE_CSC_ANALOG_CLAMP_SD_NTSC            = 2,
	SGKS_VIDEO_SOURCE_CSC_ANALOG_CLAMP_SD_PAL             = 3,
} sgks_video_source_csc_clamp_info_e;

typedef enum sgks_video_source_status
{
	SGKS_VIDEO_SOURCE_STATUS_IDLE = 0,
	SGKS_VIDEO_SOURCE_STATUS_RUNNING = 1,
	SGKS_VIDEO_SOURCE_STATUS_SUSPENDED = 2,
} sgks_video_source_status_e;

typedef enum sgks_video_source_csc_path_info
{
	SGKS_VIDEO_SOURCE_CSC_DIGITAL = 0,
	SGKS_VIDEO_SOURCE_CSC_ANALOG  = 1,
	SGKS_VIDEO_SOURCE_CSC_HDMI    = 2,
} sgks_video_source_csc_path_info_e;

typedef struct sgks_video_source_csc_info
{
	sgks_video_source_csc_path_info_e     path;
	sgks_video_source_csc_mode_info_e     mode;
	sgks_video_source_csc_clamp_info_e    clamp;
} sgks_video_source_csc_info_s;

typedef union
{
	struct
	{
		u32 v                  : 14;   // [13:0]  vertical size/position
		u32 reserved1          :  2;   // [15:14]
		u32 h                  : 14;   // [29:16] horizontal size/position
		u32 reserved2          :  2;   // [31:30]
	} s;
	u32 w;
} VdHV;

typedef struct
{
	u8  digital_out_mode;
	u8  digital_in_mode;


	u8  clk_per_pixel;
	u32 lcd_screen_width;
	u32 lcd_screen_height;
	u32 frameRate;
	u32 vout_a_format;
	u32 vour_a_freq;
	u32 offset_width;
	u32 offset_height;
	u32 frame_height;
	u32 frame_width;


	u32 hs_back_porch_min;		//THBP
	u32 hs_back_porch_typ;
	u32 hs_back_porch_max;
	u32 hs_front_porch_min;     //THFP
	u32 hs_front_porch_typ;
	u32 hs_front_porch_max;
	u32 vs_back_porch_min;		//TVBP
	u32 vs_back_porch_typ;
	u32 vs_back_porch_max;
	u32 vs_front_porch_min;		//TVFP
	u32 vs_front_porch_typ;
	u32 vs_front_porch_max;


	u8  interlace;
	u32 H_active_start;
	u32 H_active_end;
	u32 H_end;
	u32 V_Active_Start;
	u32 V_Active_End;
	u32 V_end;
	u8 d_clk_edge_sel;

	//ADD CVBS
	u32 cvbs_output_width;
	u32 cvbs_oupput_height;

} VOUT_DISPLAY_PARAMS_S;

typedef union
{
	struct
	{
		u32 format             :  5;   // [4:0] Fixed Format Select
		// 0x00: disabled
		// 0x01: 480i60 (DVE when mode 11)
		// 0x02: 480p60
		// 0x03: 576i50 (DVE when mode 11)
		// 0x04: 576p50
		// 0x05: 720p60
		// 0x06: 720p50
		// 0x07: 1080i60
		// 0x08: 1080i50
		// 0x09: 1080i48/1080psf24
		// 0x0a: 108p60 (mode 10 only)
		// 0x0b: 1080p50 (mode 10 only)
		// 0x0c: 1080p24 (mode 10 only)
		u32 interlace          :  1;   // [5:5] used if format == 0
		// 0: progressive mode
		// 1: interlace mode
		u32 reverse            :  1;   // [6:6] reverse video data horizontally
		u32 reserved           : 17;   // [23:7]
		u32 bypass             :  1;   // [24]
		u32 sync_to_vout       :  1;   // [25]
		u32 sync_to_vin        :  1;   // [26]
		u32 digital_out_en     :  1;   // [27]
		u32 analog_out_en      :  1;   // [28]
		u32 hdmi_out_en        :  1;   // [29]
		u32 dve_reset          :  1;   // [30] reset the DVE section
		u32 reset              :  1;   // [31] reset the display section
	} s;
	u32 w;
} VdCtrl;

typedef union
{
	struct
	{
		u32 d_hsync_pol        :  1;   // [0:0] Digital Hysnc Polarity
		// 0: Hsync assrted low
		// 1: Hsync assrted low
		u32 d_vsync_pol        :  1;   // [1:1] Digital Vsync Polarity
		// 0: Vsync assrted low
		// 1: Vsync assrted low
		u32 d_clk_divider      :  1;   // [2:2] Digital Clock Divider
		u32 d_clk_div_en       :  1;   // [3:3] Digital Clock Divider Enable
		u32 d_clk_edge_sel     :  1;   // [4:4] Digital Clock Edge Select
		// 0: Output value valid on rising edge
		// 1: Output value valid on falling edge
		u32 d_clk_dis          :  1;   // [5:5] Digital Clock Disable
		u32 d_clk_div_width    :  7;   // [12:6] Digital Clock Divider
		//        Pattern Width - 1
		u32 reserved           :  8;   // [20:13]
		u32 lcd_seq_even_ln    :  3;   // [23:21] LCD sequence Even Lines
		u32 lcd_seq_odd_ln     :  3;   // [26:24] LCD sequence Odd Lines
		// 0: R->G->B->R->...
		// 1: R->B->G->R->...
		// 2: G->R->B->G->...
		// 3: G->B->R->G->...
		// 4: B->R->G->B->...
		// 5: B->G->R->B->...
		u32 d_output_mode      :  5;   // [31:27] Digital Output Mode
		// 0: LCD - single color per pixel
		// 1: LCD - 3 colors per pixel /wo dummy
		// 2: LCD - 3 colors per pixel /w dummy
		// 3: LCD - 5:6:5 mode
		// 4: 656 mode
		// 5: 601 mode (16 bits)
		// 6: 601 mode (24 bits)
		// 7: 601 mode (8 bits)
		// 8: bayer pattern
	} s;
	u32 w;
} VdDigitalOutputMode;



typedef enum
{
	SGKS_VO_CLK_13_5M    = 0,
	SGKS_VO_CLK_27M    ,
	SGKS_VO_CLK_60M,
	SGKS_VO_CLK_72_25M,
} SGKS_VO_CLK_TYPE_E;


typedef struct sgks_vo_dev_info
{
	unsigned int                        irq;
#if 0
	sgks_vo_video_source_s                video_source;
	sgks_irq_callback_t                   *irq_callback;
	sgks_vo_dsp_cmd                       *pdsp_cmd_fn;
	spinlock_t                          lock;

	u32                                 irq_counter;
	struct proc_dir_entry               *irq_proc_file;
	struct sgks_sync_proc_hinfo           irq_proc_hinfo;

	u32                                 irq_wait_reset_counter;
	u32                                 irq_wait_reset_flag;

	wait_queue_head_t                   irq_wait_reset;
	wait_queue_head_t                   vsync_wq;

	spinlock_t                          wait_num_lock;
	int                                 wait_num;
	unsigned int                        timeout;

	struct sgks6802_async_proc_info       event_proc;
	struct sgks_event_pool                event_pool;
#endif
	//sgks_vo_source_status_e            pstatus;    /* Status before suspension */
	sgks_vo_source_status_e               status;
	sgks_vio_src_video_info_s              video_info;

	sgks_dsp_cmd_vo_mixer_setup_s         mixer_setup;
	sgks_dsp_cmd_vo_video_setup_s         video_setup;
	sgks_dsp_cmd_vo_default_img_setup_s   default_img_setup;
	
	u32                                   osd_setup_flag;
	sgks_dsp_cmd_vo_osd_setup_s           osd_setup;
	sgks_dsp_cmd_vo_osd_buf_setup_s       osd_buf_setup;

	u32                                   osd_clut_setup_flag;
	sgks_dsp_cmd_vo_osd_clut_setup_s      osd_clut_setup;
	sgks_dsp_cmd_vo_display_setup_s       display_setup;
	sgks_dsp_cmd_vo_tv_setup_s            tv_setup;
	sgks_dsp_cmd_vo_reset_s               reset;

	u32                                   csc_setup_flag;
	sgks_dsp_cmd_vo_display_csc_setup_s   csc_setup;
	u32                                   dram_tv_flag;
	sgks_dram_tv_s                        dram_tv;

	sgks_dram_display_s                   dram_display;
	u32                                   *dram_clut; 
	sgks_dram_osd_s                       *dram_osd; 
	sgks_dsp_cmd_pip_config_default_s     pip_config_default;

    //user set//
	sgks_vo_deviceInfo_s                  vo_user_param;
    
	
} sgks_vo_dev_info_s;


int sgks_mpi_vo_pip_config(sgks_vo_dev_info_s *pinfo);


#ifdef  __cplusplus
}
#endif


#endif




